This invention relates to a CMOS integrated circuit for signal delay which is capable of realizing an effective IC pattern when integrating delay circuits for binary signals by using CMOS (complementary metal oxide semiconductor) gates and which is capable of reducing waveform distortion (undesired fluctuation in time base) in a delayed output in the integrated circuit.
In a CMOS gate circuit, as shown in FIG. 2, a P-channel MOS-FET 12 and an N-channel MOS-FET 14 are connected in their gates and drains respectively to each other, power source voltages V.sub.DD and V.sub.SS are respectively applied in sources, signals are applied at the gates via an input terminal 13, and inverted signals of the input signals are taken out from an output termlnal 15 via drains.
A delay time occurs between input and output in such a CMOS gate circuit 10. As shown in FIG. 3, the delay time depends on the power source voltage V.sub.DD -V.sub.SS, and the smaller the power source voltage V.sub.DD -V.sub.SS is, the larger become the delay time and the rate of change. This is because the conductance of elements varies depending on the value of the power source voltage V.sub.DD -V.sub.SS. The delay time therefore can be controlled at a desired value by selecting a suitable power source voltage, utilizing the above characteristics.
The signal delay circuit with CMOS gate circuit 10 of this type is applicable , for instance, in techniques for delaying pulse-frequency modulation (PFM) signals including analog data in time base (e.g. absorption of jitter or of fluctuation in time base among reproduced video signals in a video disc playback device). More particularly, reproduced video signals including jitters are applied at a CMOS gate circuit, color bursts are extracted from the video signals outputted from the CMOS gate circuit, the extracted signals are compared in phase with a crystal oscillated clock of 3.58 MHz corresponding to the subcarrier of the color bursts to derive a phase error, and the power source voltage V.sub.DD -V.sub.SS in the CMOS gate circuit is controlled in accordance with the phase error to thereby output video signals from the CMOS gate circuit from which jitters have already been absorbed.
When a long delay time is required, CMOS gate circuits 10 should be connected in series as shown in FIG. 4. When they are integrated as ICs, power source lines 16, 17 could become wired over a long distance. By integration, however, as the width of the power lines 16, 17 decreases and the impedance of the lines accordingly increases, power source voltage changes unexpectedly to cause the delay time control to become unstable.
This invention attempts to solve such a problem by folding a continuous pattern of CMOS gate circuits in multiple-stage connection as is described in more detail hereinafter.
Folding of such patterns, however, may cause the following inconveniences:
(1) When simply folded, difference occurs between a delay time T.sub.r at a rise portion of an input waveform and a delay time T.sub.f at a fall portion thereof to cause distortion in output waveform (change in duty). With such a defect, the circuit will not be usable for video signal having data in time base reproduced from a video disc.
(2) The upper limit of operable frequency is lowered at folding portion due to the decrease of current supply capacity.
(3) A large number of CMOS gates are actuated at the same time to respond to a periodic input signal to often cause an unexpected voltage drop by the concentration of the operating current. This makes the delay time control unreliable.